Japanese Patent Kokai Publication No. JP2009-170650A describes arrangement of circuit cells and power supply lines of a semiconductor device using an MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) technique (hereinafter referred to as “power gating”). Further discussion of the power gating can be found in commonly assigned, U.S. Pat. No. 5,486,774, U.S. Pat. No. 6,034,563 and U.S. Pat. No. 6,215,159.
The entire disclosures of the above mentioned Patent Documents are incorporated herein by reference thereto. The following analyses are made by the present invention.
As illustrated in FIG. 3 of the above Patent Document, based on the semiconductor device disclosed in the Patent Document, at least a total of three power supply lines of branch lines 20D and 20S and a virtual VSS line 30S need to be arranged in a single cell array (cell line). In addition, while not explicitly illustrated in FIG. 3 of the above Patent Document, normally, a signal array is arranged in a region between the branch line 20D and the virtual VSS line VSSV.
Thus, the regions that can be occupied by the power supply lines in the height direction of the cell array (in the direction perpendicular to the direction in which the cell array extends) are limited. Therefore, based on this configuration, for example, if miniaturization of circuit elements is advanced and if the size of the cell array in the height direction thereof is reduced, the regions that can be occupied by the power supply lines are accordingly reduced. As a result, resistance of the power supply lines is increased, counted as a problem.